Extended support for Stratix V FPGA, namely: - Support for GigE modes and SDI embedded transceivers; - Now support setting additional transceivers. parameters (receiver offset calibration, linear equalizer, and dynamic reconfiguration of PMA analog settings).Added debugging interface to external memory chips (Memory Interface Toolkit). The new tool reportedly allows real-time monitor the effectiveness of the memory subsystem. You can find the most efficient mode of operation of the memory controller, changing its configuration. Added debugging tool for the transceiver (Transceiver Toolkit).Improved interface channel manager allows real-time link to watch the status of receivers and transmitters. Enhanced control panel lets the channels on the fly to change the parameters of transceivers and see how it affects the system.All this enables developers to rapidly create and debug board. There was a better means of rapid establishment of the project rather than QSys SOPS Builder. Allows you to quickly connect QSys-compliant IP-Cores blocks into a single system.

Quartus II software version 11.0, the industry's number one software in performance and productivity for CPLD, FPGA, and HardCopy ASIC designs is available for download. Quartus II software version 11.0 delivers the production release of Altera's new system-level integration tool known as Qsys. The Qsys system integration tool saves time and effort in the FPGA design process by enabling faster system development and design reuse.